Part of the historical vision of programmable hardware, (typically based on some form of FPGA technology), is that the reprogrammable fabric can remain programmable in production. One reason for this vision is that it allows adaptability to future (unforeseen) changes in functional requirements. This can also be extended to enabling changes “on-the-fly”. Fast, on-the-fly reconfiguration can also enable the re-use of FPGA logic functionality for different purposes, from moment to moment and during normal execution to implement any of a number of custom logic functionalities, thereby increasing the effective silicon density of the FPGA. Changes on-the-fly allow the personality of the logic to be altered from moment-to-moment as different algorithms are required for different tasks, sometimes altering the personality in as little as a clock or two. The faster the FPGA can be reconfigured, the more its resources can be utilized for more than one user function, and the more the effective density is increased. This fast reconfiguration for increasing effective silicon density is especially useful in DSP (Digital Signal Processor) applications where many large multiplier functions are typically required, but if connected differently from moment to moment, can be re-used to implement different algorithms as required.
Conventional FPGA devices like those manufactured by Xilinx and Altera have been enhanced to allow somewhat faster reconfiguration and/or also partial reconfiguration. Also, some FPGA fabrics (the basic logic array structure) for use as IP (Intellectual Property) Cores in System On Chip (SOC) designs have been designed with provision for very fast full and/or partial configuration. However, these enhancements usually do not allow for major functionality changes within a clock or two. Even so, FPGA fabric providers like Elixent and Adaptive Silicon see their fast reconfiguration capability as valuable for re-using FPGA logic for different algorithms in the same application. Also, companies like PACT and GateChange see their fast partial-reconfiguration capability as useful for changing functions in real-time in a pipelined manner, so that the FPGA function can be altered as data propagates through the device. Chameleon offers a device that contains a full shadow memory for fast reconfiguration in a clock or two.
Unfortunately, the FPGA fabrics typically used in these solutions consume between 20 and 40 times as much silicon area as a standard-cell ASIC implementation normally used in high-volume SOC design. Very fast reconfiguration capability that is implemented without adding large amounts of additional memory requires an FPGA fabric architecture that has additional silicon area allocated to fast reconfiguration bus structures and sometimes additional memory to cache some of the reconfiguration data. Further, if it is desirable to alter the function of the FPGA fabric on-the-fly and within a clock cycle or two, additional configuration memory must be included in the FPGA fabric to implement the “multi-program” capability, increasing the consumption of silicon area even more.
Today, it remains to be seen if the value of full reprogrammability is economically viable for high-volume designs. The same is true for fast-reconfiguration FPGAs for multi-program implementations where full reprogrammability is retained for each personality (custom logic functionality)—regardless of whether additional configuration memory is included or not. The silicon area penalties of retaining the capability for FPGA fabrics to implement any arbitrary functions are too great for most applications with any significant production volume.
There may come a time where fully-programmable multi-program (fast reconfiguration and/or multi-program memory) FPGA fabrics may become viable for SOC and FPGA volume production. However, in the meantime, there is a need for solutions that take advantage of the flexibility benefits of FPGA technology, while also providing an effective and practical solution for volume production. The promise of fast reconfiguration in FPGA fabrics for the purpose of re-using silicon resources (like arrays of large multipliers in DSP applications) may be fulfilled with acceptable device cost if the fabric can be tailored to the application.
Also, given the realities for very deep submicron design and the opinion of some experts that Moore's law (for semiconductor density and performance over time) is breaking down, it would be especially valuable if a device architecture were available that can implement multi-program functionality for a particular customer application, with acceptable silicon area for volume production, while requiring a limited number of custom masks for personalization.